FPGA Overhead Costs

FPGAs carry much overhead which is eliminated when the customer converts to an ASIC chip. The overheads include elements such as:

Process Overheads:

FPGA never reaches the process maximum frequency due to routing. Average frequency capability is about ¼ to ½, which is equivalent to an ASIC manufactured in an earlier (and cheaper) process technology node.

Production Overheads:

Area Overheads:

Logic: Each CLB is built of LUTs, FFs and glue logic which are set to a single binary function. This structure actually wastes a lot of unused area.
Routing: Placement of internal blocks is arranged in vertical tiles. This structure makes the routing longer, heavier and much less efficient than ASIC routing.
Routing: Each routing switch point is built out of six pass transistors, which do not exist in an ASIC chip
Routing: Wires are longer compared to an ASIC, and therefore require extra buffers to handle large fan-out trees
Utilization: FPGA logic utilization never reaches 100% capacity. Average capacity usage is 75%; the rest of the logic exists but is not used.
Utilization: FPGA hard blocks, such as memories, DSPs, I/Os, etc., are not used up to 100%
Configuration: The FPGA programming file uploaded on power-up uses an internal large configuration SRAM, which does not exist in ASIC
Configuration: The FPGA has an internal boot loader and an internal debug infrastructure.

System Overheads:

Additional EPROM / FLASH to store stream bits, and several units for high gate count FPGA
High package cost: Most FPGAs are supplied with a high pin count BGA package, which is not needed for most applications. In addition, the package cost is affected by the FPGA's high power consumption and special assembly materials and processes.
The FPGA uses external multi voltage supplies: 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1.0V, which require extra regulators