|
Performance improvement case studies:
1) Based on table from: "FPGA for DSP: A JPEG Encoder Case Study" by Scott Thibault, Green Mountain Computing Systems, Inc.
|
Platform
|
JPEG Performance
(blocks/second)
|
|
TI C5410 (160MHz)
|
6835
|
|
Blackfin (300MHz)
|
12602
|
|
Blackfin (750MHz)
|
31505
|
|
FPGA (Impulse C)
|
41025
|
| KaiSemi ASIC1 (250Mhz) 0.13um * |
205125
|
|
KaiSemi ASIC2 (450Mhz) 0.09um *
|
369225
|
* Estimated performance based on speedup from 50Mhz FPGA.
2) Based on table from: "High-Performance DSP Capability Within an Optimized Low-Cost FPGA Architecture" - A Lattice Semiconductor White Paper .
|
Device
|
Clock Speed
|
Number of Multipliers
|
MMAC/sec
|
1K Unit Cost*
|
Cost per MMAC/sec
|
|
TI DSP
|
1GHz
|
4
|
4000
|
$256
|
¢6.4
|
|
TI DSP
|
300MHz
|
4
|
1200
|
$40
|
¢3.3
|
|
ECP-DSP20
|
250Mhz
|
28
|
7000
|
$59
|
¢0.8
|
|
KaiSemi ASIC1
|
250Mhz
|
476
|
119000
|
$29
|
¢0.024
|
|
KaiSemi ASIC2*
|
450Mhz
|
476
|
214200
|
$59
|
¢0.027
|
* Estimated performance based on speedup from 250Mhz FPGA coupled with ability to scale parallelism by a factor of 17.
KaiSemi ASIC1 is a cost reduction chip (price is estimated and may be considerably lower).
KaiSemi ASIC2 is an accelerated version with more processing power.
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