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Technology | Conversion Process
Conversion Process

FPGA Conversion

FPGA conversion was introduced for many reasons, including::

  • Cost reduction – Enabled by smaller silicon size, due to major reduction of extra “junk" logic; the use of earlier process nodes and cheaper ASIC technology; an equivalent or better performance and high volume production.

  • Performance improvements – Shorter paths in the ASIC and optimized logic lead to similar or higher performance.

  • Lower power consumption – Dramatic reduction in the transistors count (50% and more) naturally leads to reduced power consumption.

  • Lower EMI – Compared to FPGA devices, ASICs involve lower EMI

  • Higher volume production

 

Traditional FPGA Conversions Vs. KaiSemi’s Offering

The phrase ‘FPGA conversion’ is widely used in many contexts without always the true meaning behind it. Most if not all of the services provided these days under the title “FPGA netlist conversion” basically take the RTL code as a source for starting the so-called "netlist conversion". Such a process is practically similar to starting a regular RTL ASIC design flow with all the costs and the risks involved. Additional setbacks might include long lead times, costly re-spins and reworks, due to the fact that the RTL was never really proven at real time working conditions. Under such circumstances, the designers’ ability to achieve effective functional test coverage using the available RTL-oriented test benches is no more than 20% in comparison to chips which are tested in real-time working hardware environment. The limited resources available for simulation tests also restrict the number of clock cycles which practically run on the full RTL chip design.

Contrary to these examples, the FPGA chip, including its netlist, has been proven in a real time working hardware system. Thus, billions of clock cycles, virtually unlimited, have run and verified almost all possible scenarios of the required chip functionality in board, system and product level. This fact provides the customer with the confidence to freeze the FPGA design. The whole process has required significant time, efforts, adjustments and fine tuning. The FPGA netlist which has been created as a result is different in many aspects from the original RTL code.

KaiSemi is unique in its approach to FPGA-to-ASIC conversion. We focus solely on the Post Compiled FPGA Verilog netlist and the SDF, which are used for simulations and STA verifications in common tools.

We do not take the RTL for conversion.

We use only the post compiled Netlist for any size of FPGA and we support most of the FPGAs available at the market.

This approach allows us to provide the customer with a functionality guarantee for the resulting ASIC device. In case the ASIC chip doesn't work, the customer doesn't pay. On top of that, the KaiSemi approach shortens the lead times for prototype to a few weeks and reduces the risks incurred by the customers through various means, including KaiSemi’s ZERO NRE model for project kick-off.

Customer Deliverables

The main files we receive from the customer are:

  • Post compiled, final/frozen, Verilog netlist and SDF – used for reference simulations and for the conversion process itself

  • Functional vectors – extracted from the customer test benches. Used as a general guideline and indication for the correct operation of the customer provided files as well as for the reference simulations during the conversion flow.

  • PIN file – a matrix which details signals locations, external hardware interface characteristics and various external hardware interface requirements

  • Customer checklist – includes extra engineering info on the design such as timing constraints, clock frequencies, required DFT (SCAN, JTAG, BIST…) and related parameters

  • Customer package marking form – includes the marking on the final ASIC, such as chip number, logo and other descriptors.

 

KaiSemi’s Flow Overview

Several steps in KaiSemi’s flow differ from regular ASIC flow: In addition to commonly-used EDA tools, the process is based on KaiSemi’s proprietary tools dedicated to the netlist conversion flow.

The tools were developed based on extensive accumulated knowledge and experience covering over 500 conversions during the last 13 years.

The tools dramatically accelerate the conversion process and allow KaiSemi’s engineers to validate the conversion flow by using multiple diagnostic tools and cross checks along the path.

Figure 1 describes KaiSemi’s FPGA-to-ASIC conversion flow: