istock_000005279712small.jpg
Solutions | FAQ
FAQ

Frequently Asked Questions 

Who is KaiSemi?

KaiSemi is a fabless semiconductor vendor that specializes in selling replacement chips based on automated conversions. The company's conversions portfolio includes FPGA-to-ASIC, Multichip-to-ASIC, ASIC-to-ASIC, and DSP algorithm-to-ASIC.

KaiSemi's FPGA-to-ASIC conversion offering is complemented by additional capabilities. For example, the company can convert multiple FPGAs into a single ASIC die. KaiSemi can also add peripheral die (such as memory) stacked with the FPGA replacement die in a single package. KaiSemi handles ASIC-to-ASIC conversions, mainly for End-of-Life purposes. Additional offerings include migrating DSP algorithms to ASIC implementations via FPGA evaluations and prototypes.

KaiSemi's business model is based on selling drop-in replacement chips at a reduced cost with no NRE, based on quantities. Each FPGA-to-ASIC conversion project quantity order covers the total one-time ASIC expenses while remaining significantly cheaper than the original FPGA chip order.

KaiSemi officially joined the Kai-Tek Group in late 2009. The company's founders and leaders originate in Flextronics Semi & AMI Semi, where they specialized in VLSI, ASIC, EDA, and conversion-related fields. The team members' experience includes more than 500 successful conversions of FPGA/ASIC components.

KaiSemi is a daughter company of the Kai-Tek Group, which was established in 1996. The Kai-Tek Group is a leading Israeli representative and distributor of electronic and semiconductor components. The Kai-Tek Group also acts as a design house turnkey provider and as an electronic assembly manufacturer. Kai-Tek has been representing Toshiba Semiconductors and fab since 1998. The company's strong financial footing is backed up by impressive revenues during the last 10 years.

How does KaiSemi's Zero-NRE model for FPGA-to-ASIC conversions work and how can you afford it?

The "Zero-NRE" model means that the customer doesn't pay in advance for the one time design cost known also as NRE (Non Recurrent Engineering). The customer places a purchase order for the chips as if they were "off-the-shelf" chips without considering NRE.

Technically, our ability to offer a Zero-NRE model is associated with the functional guarantee we provide. The functional guarantee is possible because there is no RTL touch and no human errors during the automated conversion phase – a process which is handled by a highly experienced team.

After the customer accepts the quote for the desired quantities, the first order for which the customer delivers a Prototype-Approval-Conditioned-PO (Purchase Order) is placed before we start to work and is actually the conversion project kick-off.

After the stated lead-time, we provide 10 prototypes, in order to let the customer approve the functionality. Once approved, production starts and the first batch of the first order is then shipped according to the agreed terms.

For any additional order beyond the first order, we'll provide the goods based on the original quote for the "next order". We provide an end to end solution – we ship finished goods in any format: packaged, bare die, T&R, tubes or any other method requested by the customer.

Usually, our model offers a price per final replacement good chip with No NRE charge. We take into account all the NRE expenses including the minimum order lot and calculate them into the chip price accordingly. We find the chip price where a defined quantity of the replacement ASIC chip should be cheaper (or even much cheaper) compared to the FPGA chip price. The minimum quantity that represents this price is the breakeven point for preferring an ASIC replacement chip over the original FPGA. If your target is cost, then there is no question about it: you need to pass the breakeven point of minimum quantity.

 

Since we sell the replacement chips and not the conversion service, the quote is highly associated with the quantity you can commit to produce (you can refer to yearly quantity). As a result, the customer enjoys both the easiness of placing a purchase order for an "off-the-shelf" 2nd source replacement chip and the fast lead-time and seamless process that our unique automated conversion tool can offer.

 

What are the work stages in your FPGA-to-ASIC projects?

1.  The quote stage:

KaiSemi receives the project FPGA netlist from the customer. It then performs only the automated conversion that is required to define the cheaper fab process technology that fits the device, the optimal die size and the breakeven point for minimum quantities.

Based on the customer's requested quantities, the conversion's outcome, the calculation of all pricing parameters and KaiSemi's detailed fab pricing tables, KaiSemi provides a quote.

 

Another option is to have KaiSemi provide an estimated quote with +/-15% variation. This option is applicable in case the only available information is KaiSemi's quick RFQ which is filled by the customer instead of providing the netlist. This option allows the customer to quickly understand whether his project is in the ASIC worthy zone. The customer can also quickly estimate the amount of money he can save, without the need for a higher management decision to release the netlist out.

 

In addition to the quote, once KaiSemi receives the netlist and performs a preliminary conversion, KaiSemi can provide an estimated power consumption of the final ASIC.

 

2.  The order stage:

Once price and quantities are set, the purchase order is accompanied with an agreement which states that no NRE is involved and that KaiSemi is obligated to provide the customer with a functional guarantee. The functional guarantee obliges KaiSemi to perform re-spins on its account in case KaiSemi causes a different functional behavior compared to the original FPGA. It also obliges the customer to pay the first purchase order payment, which means that it is a non-cancellation order. The first order is used by KaiSemi to cover its prepaid NRE expenses.

 

Once the agreement is set and signed, the down payment for the first order is made and the conversion project kicks off. KaiSemi expects to receive a netlist, functional test vectors, constraint file, pin file and KaiSemi's checklist file. Once all inputs are checked and verified, KaiSemi starts its flow on a fast posted mode, all the way until prototype delivery. During the process it informs the customer on the progress status.

 

3.  The ASIC product stage

KaiSemi delivers 10 final ASIC prototype parts to the customer after the defined lead-time. The customer is required to assemble the replacement part in his real system or in his lab test environment and check if the functional behavior acts the same as the original FPGA part. We expect this qualification period to end within 1 month. Once approved by the customer, the first order starts to be manufactured and shipped according the agreed set of batch orders within the agreed period of time, where payments are accepted accordingly.

How much do I save by converting my FPGA to an ASIC?

Usually, the cost of the first order is already 40%-50% cheaper and the cost of the second order is 60%-70% cheaper in comparison to the FPGA. So you get a cheaper chip with No NRE, based on quantities. And today, minimum quantities are not high. 

What are the typical lead times of the design process?

The lead time, from kick-off to samples, is between 8 and 22 weeks. The exact lead time depends on the manufacturing process and on the complexity of the design. For 500nm process it takes about 8-10 weeks, for 350nm process it takes about 10-12 weeks, for 180nm process it takes about 12-15 weeks, for 130nm process it takes about 15-18 weeks and for 90nm process it takes about 18-22 weeks.

How can you offer a "No Good, No Pay" model for your chips? 

With massive experience of more than successful 500 conversions, we feel very comfortable delivering first spin working silicon.

The "No Good No Pay" model is a result of the functional guarantee we provide for the replacement chip. The model means that we take the risk incase the replacement ASIC chip doesn't work: We find the problem and perform and pay for the re-spins until the ASIC chip works.

Once we provide the prototypes to the customer, we expect the replacement chip prototype to be checked by the customer within an agreed time limit. The customer has to run the ASIC in the relevant real system and approve that the functionality works the same as the original FPGA product part. Once this confirmation is received, the mass production order can be placed.

How is KaiSemi's solution different from traditional ASIC flow? 

The fact that we offer a unique auto conversion directly from FPGA netlist provides us with major benefits over others:

1.       Fast ASIC cycle – about half the time compared to a typical process

2.       No RTL touch – ensures quality in a way which enables us to provide functional guarantee (No Good No Pay and No NRE). Our automated tool involves no functional touch. This is the basis for the functional guarantee we give and for the ability to shorten time to product through a process which is seamless to the customer.

3.       Automated process -fast flow with minimum potential human errors also leads to functional guarantee (No Good No Pay and No NRE)

4.       Minimum to zero intervention needed by the customer during the conversion – a process which is seamless to the customer

5.       The optimization uses a database of five different processes licensed from our Toshiba fab partner.

 

How is KaiSemi's solution different from Structured ASIC solutions?

1.       Structured ASIC fits only low quantities, and even in this case, prices could be higher than ours.

2.       In structured ASIC, the mask templates are in fixed sizes and in fixed fab process nodes, since they are prepared in advance. As a result, die size is bigger by default compared to a more expensive fab process, which leads to a higher manufacturing cost while their NRE mask cost is lower. Nevertheless, the routing metals of the Structured ASIC are not predefined and have to be designed per project, which means that routing mask set cost is about 1/3 of the total mask set.

3.       Structured ASIC processes sometimes involve additional downsides, such as the need to perform a full ASIC flow cycle starting from the RTL sources, without the type of benefits offered by KaiSemi, i.e., automated, fast and seamless netlist conversion.

 

How about embedding cores?  Do you depend on the fab to provide the license?  If so, what cores are available from the fabs?

For soft IPs, there is no dependency on the fab. For general hard IPs like memories, DSPs and LUTs, there is also no dependency on the fab. For special hard IPs like PCIe and SerDes we do need to find a replacement, which is usually available, as part of the offering of large fabs.

Technically, our conversion cannot tell if there is a soft IP inside the design, since our conversion tool deals with flattened gate-level to gate-level. Theoretically, if the customer doesn't reveal whether he's using a soft IP, we will not know. Naturally, it won't have any effect on the conversion process.

From a business perspective, a customer that uses a soft IP that is licensed to use it only in FPGA, has to deal with the vendor from which the soft IP had been purchased, for licensing it to ASIC.

As for Hard IPs, these blocks are replaceable since we use standard-cell libraries in 5 different fab processes that cover the entire FPGA type range. Third party standard I/O cores IPs are offered to be used as part of the processes we use. Our solution, which allows standard ASIC process, enables us to use existing third party hard macros. We deal with creating a wrapper to fully fit the core configuration.

Note that we replace hard macros I/Os which are standard interfaces, but we don't replace special/non-standard hard IPs, such as embedded hard controllers; instead, we offer the customer to replace them with the soft IP version.

 

We can roughly split the FPGA hard macros to the four following categories:
1. Hard macros I/Os of the external interface (i.e. DDR, HSTL, LVDS, etc.): As mentioned above, we replace those macros I/Os with a proven macro from the fab library.
2. Hard macros of Phys of the external interface (i.e.  PCIe, Phy): Those complex Phys involve a group of 2.5G/5G SerDeses, and we replace them with a proven macro from the offered fab library, while building a wrapper around it, in order to fit the FPGA parameters that were used. Such a step will require extra expenses on our part; since we buy the needed elements in addition to our library licensing, and we calculate them into the chip price.
3. Embedded hard macros which are native in each project (PLL, memory, multiplier accumulators, POR, etc.): We replace those macros with a combination of owned soft logic IPs, wrappers and proven macros from the fab library (when required).
4. Special embedded hard macros (i.e. DRAM controller, PCIecontroller, Power-PC, Ethernet-Mac, etc.): As mentioned above, for those elements we offer using a purchased soft IP and then convert it with our regular gate-level conversion (these elements are mainly used for evaluation, where in our business model ,which is based on mass production, companies are unlikely to use these elements).


Which foundries and process technologies do you target?

Technologies:  

Our database covers full ASIC flow sets for each of the following processes: 90nm, 130nm, 180nm, 350nm and 500nm (covering ALL FGPA families).

All of these processes are well established in our database. For each process we have a variety of libraries that enable us to select an optimized process in terms of cost or power according to each project's requirements.

Business: 

We have a business relationship with Toshiba. We also support other fabs such as TowerJazz, NEC, UMC and SMIC

Which wafer sizes do you use?

We mainly use 8" wafers since they are the most common and provide best value for money. Nevertheless, we also support 6" wafers at500nm and 12" wafers at 130nm and 90nm.

Which ambient temperatures do you support?

We support commercial temperatures of -20°C to 70°C (-4°F to 158°F) and industrial temperatures of -40°C to 100°C (-40°F to 185°F)­. We are of course capable of supporting extended temperature.

 

How do you handle timing closure? 

 

Timing is closed pretty easily, since FPGA technology involves huge overhead in timing, due to the massive amount of routing, junction's logic, configuration logic, control logic and fan-out buffers on both the nets and the clock trees in addition to the extra unused embedded hard macro blocks such as extra RAMs, DSPs, FIFOs, etc. When you go to an ASIC hardening the clock trees are dedicated to a design and achieve much better size and skew. Additionally, the logic area is shrunk by around 90% (from the transistors count point of view), a fact which also eases the handling of timing.

On the replacement ASIC, timing is identical to the original FPGA. We replace the PLLs to other PLLs with the same output constraints. We build a new clock tree with a better skew and check the crossing points between clock domains with a CDC tool. We make sure there is no timing violation. We even support industrial and military grades.

 

Why does the power consumption improve? 

Since the logic area size is reduced by 90%, power consumption is reduced. Since we opt for a cheaper fab process compared to the original FPGA fab process, power achieves less than 90%. The range is somewhere between 0% and 80%, where the tradeoff is with the chip cost.

 

Additionally, we use low power fab libraries, where you have to take into account a tradeoff with timing.

 

Are we allowed to convert FPGAs?

Performing FPGA conversion into ASIC is totally normal and legal practice.

The netlist that we use in order to start our progress is a standard Verilog file netlist that is provided to each FPGA user for external use as for gate-level simulations, gate-level editor, timing checks, etc.

In our process we don't use any IP owned by the FPGA manufacturer, not even partially, and we don't use any part of the FPGA manufacturer's software. Our process handles the logic part on the digital function level without using any FPGA atom.

The Verilog netlist file itself is an IP that belongs to the FPGA user and includes the user's confidential functional design. The customer is entitled to use it as long as it serves him and we do not use it for anything except for the customer.

How do you cope with the legal issues in soft IP blocks?

For each soft IP, we make sure that the customer upgrades his license with the IP vendor to an ASIC license. These legal aspects are considered most important and are taken into account.

Do you compete with ASIC design houses? 

We do not. We are not a service company, but rather a replacement chip provider.

We provide a full turnkey solution from a working FPGA chip to a working replacement ASIC chip, in a seamless and guaranteed way.

The ASIC companies you're referring to offer a traditional design house service starting from the RTL flow with NRE cost and other overheads.

You can convert the functionality of an FPGA into an ASIC, but how can you duplicate the exact I/O characteristics?

We don't need to duplicate I/O characteristics, because I/O interfaces are all standard and exists in the market for standard-cell fab processes. We use standard replacement I/O cores from the proven fab libs that we're licensed to. We don't "invent the wheel"; these are existing cores. What we did was to open the door for a conversion like ours to use the wide existing standard offering.

How can you guarantee that your ASIC is functionally compatible with the original FPGA?

Our IP tool is dedicated to this purpose. It was developed based on vast knowledge and experience in netlist conversions. These assets were gained over 10 years and through 500 successful FPGA-to-ASIC conversions, which our team has performed during our past work at Orbit Semi, Flextronics Semi and AMI Semi conversion divisions.

The conversion is based on an automated operation while using a preinstalled database that was embedded in the tool's conversion process and tested. Additionally, the conversion operation doesn't involve RTL touch, a fact which enables us to produce a reliable outcome.

While at previous companies we had done gate-array only, we now take it to a different level by supporting standard-cell libraries provided by the fab itself, an arena where there is also a huge offering of usable IP cores.

How do you deal with PCIe cores?

The PCIs cores involve two parts: the PCIe Phy hard macro and the PCIe embedded controller. The PCIe Phy is a standard core and we can use the fab's PCIe core since it is part of their offering where we, in addition to buying it, need to fit it with a wrapper. We don't replace the embedded controller PCIe with a hard version, but offer the customer to use a soft version instead. These embedded macros are not common in large volume products, since they limit product upgrades.

Does KaiSemi support SerDes hard macros?  

SerDes is a standard I/O interface core which is offered, per selected process, by the fab lib that we're licensed to. We fit it to the same constraints with a wrapper. As explained above, we opened the door to be able to use existing 3rd party offering within the conversion. We surely don't copy anything what so ever from the FPGA.

What would you need in order to quote?

There is a short – few questions only - RFQ form (based on the FPGA report file) to which we respond by providing a quick quote estimation (+/-15% accuracy) within 1-2 working days. Another option is pulling out the Verilog netlist (which is very easy). Once we receive it, we can provide an accurate quote.

Are there any obstacles in your process?

There are no obstacles but there are challenges. For example, Gen2 PCIe Phy is an IP replacement that we buy and would require cooperation in order to deal with the customer constraints at the FPGA Phy. We'll make sure we have the correct wrapper in the ASIC and fit the functional simulations accordingly. In the case of SerDes for example, the lead time will increase in about 4 weeks.

For Async clock design in an FPGA, which is a digital part by nature, there is usually no problem with multi-cycle constraints and with ASIC clock skew. Signals set-up times are better and the only risk in place is the Sync machine of crossing clock domains. These signals set-up times are part of the customer's functional design. In this context, a design that might seem as working in a proper way, might include hidden errors. We check clock domains crossing on a regular basis. In case we find a problem we inform the customer of the functional error or the wrong implementation.

 

 

end faq

 

Do you have any other questions?

It would be our pleasure to discuss any specific questions with you. You can contact us directly at +972-9-8920409 or via email at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .